The present invention relates to display devices and methods for controlling the display devices, and more particularly, to a display device of an active matrix type having a display driving circuit formed on a substrate of a display panel and a method for controlling the display device.
In a liquid crystal display device as one type of the active matrix type display devices, regions surrounded by two of a plurality of gate signal lines provided in a vertical direction and by two of a plurality of drain signal lines provided in a horizontal direction are formed on a surface of one of two substrates having a liquid crystal disposed therebetween which is contacted with the liquid crystal and are used as a single pixel region.
The pixel region has a thin film transistor operated by a scan signal supplied from one of the two gate signal lines and a pixel electrode to which a video signal is supplied from one drain signal line via the thin film transistor.
The pixel electrode generates an electric field, for example, between the pixel electrode and an electrode opposed thereto and formed on the other of the two substrates. The electric field is used to control the light transmissivity of the liquid crystal provided between these electrodes. Such a liquid crystal display device comprises a scan signal driving circuit for supplying the scan signal to the respective gate signal lines and a video signal driving circuit for supplying a video signal to the respective drain signal lines.
Each of these scan signal driving circuit and video signal driving circuit includes a multiplicity of MIS (metal insulator semiconductor) transistors having a structure similar to the thin film transistor formed in the pixel region. Thus, such signal driving circuits are known as having such an arrangement that a semiconductor layer in each of the transistors is made of polycrystalline silicon (p-Si) and these signal driving circuits are formed on one substrate concurrently with pixel formation.
Such a circuit as to have many polycrystalline silicon transistors has a low output voltage. Therefore, when such a low output voltage is used as it is, it may be, in some cases, impossible to obtain a necessary driving voltage.
Further, when it is assumed that a control signal (such as a clock signal) necessary to operate these circuits is supplied from an LSI or the like provided in the periphery of the substrate, and when the breakdown voltage of the LSI is low, there may occur such a situation that the low voltage of the control signal issued from the LSI causes the circuits not to be sufficiently operated. To avoid such a situation, a voltage level converter for converting a voltage such as a pulse from its low level to high is built in such circuits.
Such a voltage level converter circuit is disclosed in U.S. Pat. No. 6,686,899 (JP-A-2002-251174). The voltage level converter circuit has a feature of being capable of sufficiently suppressing a through current. In one of embodiments of the converter circuit, the converter includes MIS transistors of an identical conduction type (N or P). In FIG. 11C of the U.S. Pat. No. 6,686,899 (JP-A-2002-251174), an input terminal for an input pulse VIN is connected to a first terminal of a first MIS TFT NMOS1, an input terminal for an input pulse /VIN having an inverted phase to the input pulse VIN (“/” in /VIN denotes bar, meaning a pulse corresponding to inversion of the input pulse VIN) is connected to a gate terminal of a second MIS TFT NMOS2, a gate terminal of the transistor NMOS1 is connected to a supply side of a power source for supplying a constant voltage VDH, a first terminal of the transistor NMOS2 is connected to a supply side of a power source for supplying a low voltage VAL, a second terminal of the transistor NMOS1 is connected to a first terminal of a capacitance and to a gate terminal of a third MIS TFT NMOS3, a first terminal of the transistor NMOS3 is connected to a supply side of a power source for supplying a high voltage VAH, and a second terminal of the transistor NMOS2 is connected to a second terminal of the capacitance and to a second terminal of the transistor NMOS3, which interconnection forms an output terminal.